1. Field of the Invention
The Invention relates to the handling of interrupt signals, and more particularly, to the handling of long latency interrupt signals in a computer with an input/output (I/O) write posting capability
2. Description of the Related Art
The growth of the personal computer industry is attributable in part to the availability of low cost, yet powerful computers. Improvements in processor, memory and data storage capabilities have resulted in light-weight, powerful mobile computers such as portables, luggables, laptops, notebooks, palmtops and personal digital assistants. These computers can provide sufficient processing capability for audio visual applications such as computer aided design, three-dimensional animation, and multimedia presentation even when users are at remote locations.
Although mobile users want lightweight and compact computers for their mobile computing requirements, they also want the ability to accept a broad range of peripherals via expansion buses such as the Industry Standard Architecture (ISA) bus, the Extended Industry Standard Architecture (EISA) bus, or the Peripheral Component Interconnect (PCI) bus. However, due to weight, space and power consumption limits imposed by the physical structure of the portable computer, the portable computer cannot provide the same expandability as the desktop computer. One method of providing expandability for portable computers without sacrificing size, weight and battery life is through an expansion base unit. The expansion base unit is a non-portable unit that operates from AC power. When the user is at his or her home-base, he or she simply plugs the portable computer into the expansion base unit to access the additional peripherals. For example, the expansion unit may have a network interface card (NIC) for connecting to a local area network, a large capacity disk drive for additional data storage, and other expansion cards that do not need to be on the portable computer itself.
Although the connection between the portable computer and the expansion base unit may be accomplished via a proprietary bus, an alternate route is to connect the two units via the standard expansion bus itself to minimize translations from the standard expansion bus and back. In this manner, the expansion base unit adds a second bus that is an extension of the portables standard expansion bus, effectively increasing the number of slots available to accept expansion cards to the entire computer system. However, the possibility that peripherals on both buses can be mapped into the same addresses complicates the process of accessing individual peripherals when the portable computer is docked to the base unit because of the potential conflicts.
One such interaction involves interrupt signals. In conventional computer systems, hardware devices such as a keyboard or a serial port can request servicing on a timely basis. Although the central processing unit (CPU) can periodically poll each peripheral to ensure that requests are timely serviced, an interrupt approach is more efficient because it allows the microprocessor to execute its main program and to service peripheral devices only when requested by the device itself. The interrupt approach typically uses a programmable interrupt controller (PIC) coupled to the system bus to function as an overall manager in accepting interrupt requests from the I/O devices. In typical personal computer (PC) systems compatible with those made by International Business Machines Corporation, the PIC receives interrupts over the ISA expansion bus and appropriately pulses the interrupt input of the processor. The processor completes the currently executing instruction, issues an interrupt acknowledge signal to the PIC and then executes a service routine to service the requesting device. Once the interrupt has been serviced, the processor writes an End-of-Interrupt (EOI) input/output (I/O) command to the PIC and continues processing where it left off. The EOI command is typically sent through an I/O instruction to a register within the PIC.
In the multi-bused environment presented by the portable computer-expansion unit combination, the interrupt system must properly process the interrupts from each bus, behaving to the software as though only one bus exists to remain compatible with the vast base of software for the IBM PC. Further, the interrupt mechanism should minimize the number of signals required to be transmitted to minimize the pin-out, wiring, and connector costs associated with communicating these signals. To address these requirements, a new interrupt bus architecture known as the interrupt serial (IRQSER) bus was recently developed where peripherals and devices on ISA, EISA or PCI buses can transfer interrupt and other information from one system component to a system host controller in a time divisioned manner. Peripheral devices sample the serial bus and gate the interrupt signal onto the serial bus at the appropriate time to send their interrupt requests. In this manner, the serial bus is an independent channel apart from the ISA bus, EISA bus, or PCI bus for transmitting interrupt requests.
Although the interrupt serial bus provides a low cost method for flexibly communicating interrupt signals from a variety of sources to the interrupt controller, the serial nature of the interrupt bus creates a potential latency problem. In a typical interrupt scheme, a device asserts an interrupt request (IRQ) signal to request servicing. The IRQ signal instructs the interrupt controller to interrupt the CPU, which interrupts its interrupt service routine. The device responds by deasserting the IRQ signal, so the interrupt controller then knows the device is no longer requesting an interrupt.
But further, the interrupt controller then must also keep track of when the CPU has finished processing the current devices interrupt. It does so by maintaining a register that is written to by an End of Interrupt I/O command from the CPU, which the CPUs interrupt service routine writes immediately before exiting.
The problem arises because of the delay between when the CPU clears the devices interrupt by an I/O operation to an appropriate register and when the interrupt controller becomes aware that the device is no longer requesting an interrupt. Assume that the interrupt service routine clears the devices interrupt and then immediately sends an EOI command to the PIC. Although the device has dropped its interrupt request, that information has not passed over the interrupt serial bus IRQSER, so the interrupt controller believes the device is still asserting its IRQ signal. But then, the interrupt controller receives the EOI signal from the CPU. The interrupt controller then initiates another interruptxe2x80x94this time a spurious interruptxe2x80x94because the IRQ still appears asserted. Similar latency related problems can arise through missequencing of other device related signals to the PIC versus CPU I/O operations with the PIC. For example, the CPU may read the IRR, or interrupt request register before that register reflects a changed state of the requesting devices.
One solution to the latency problem is to delay the EOI signal (or other PIC related I/O operation) to the interrupt controller by the same amount of time as the maximum IRQSER cycle latency, ensuring that the events do not occur out of order. However, such delay is undesirable from a performance viewpoint. It is desirable that the write of the EOI command be presented to the PIC after the interrupt signal corresponding to the EOI has been cleared to ensure correct sequencing of the interrupt signal, but without unnecessarily delaying that operation.
An apparatus is provided for handling long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that I/O operations between the processor and the interrupt controller are properly synchronized to prevent false interrupts or inaccurate data from reaching the processor. Initially, the interrupt signals from various devices are serialized and transmitted over the interrupt serial bus to an interrupt controller, which interrupts the processor upon an interrupt request, causing an interrupt handling routine to be executed. At the end of the interrupt handling routine, the processor performs an I/O write of an EOI command to the interrupt controller. Upon receipt of a write operation that may be an EOI command, the controller verifies that the posting buffer for posting I/O writes to the expansion bus is empty. Such an I/O write could be the I/O operation necessary to clear the interrupt of the interrupting device. When this posting buffer is clear, the controller then imposes a pre-determined delay to ensure sufficient time for any cleared interrupt signal to be transmitted over the interrupt serial bus. Next, the controller checks the interrupt serial bus for activity. If the interrupt serial bus is idle, the I/O write operation that may be an EOI command is issued to the interrupt controller. Alternatively, the controller waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI command to be written to the interrupt controller. The back-to-back wait requirement prevents false interrupts from being generated should the cleared interrupt miss its transmission window over the current interrupt serial bus cycle, or should the cleared interrupt be delayed by any interrupt serial bus transmission latencies. System performance is thus enhanced because I/O write operations are posted. The write posting capability allows the processor to execute the next instruction while the current write operation is still occurring. Further, the ability to write EOI commands immediately after the serial bus becomes idled allows the EOI operations to be performed within one interrupt serial cycle, thus enhancing performance. In addition, by ensuring that writes of EOI commands are properly sequenced, the present invention prevents spurious interrupts from reaching the processor.
Other I/O operations with the PIC are similarly handled. When an I/O operation is directed to the PIC, it is first determined that the write posting buffer is empty, followed by a delay or by waiting for an inactive serial bus for two back-to-back cycles. In this way, the PIC will accurately reflect the state of its connected devices before it provides device related information in response to a PIC related I/O command.